Custom Edge AI Computer Design & Manufacturing

Sixfab designs, certifies and manufactures custom edge AI computers built on Raspberry Pi compute modules, with a DEEPX NPU as our validated default — and Hailo, MemryX, Axelera or NXP where the workload calls for it — plus optional LTE/5G. We are a Raspberry Pi Approved Design Partner and act as hardware manufacturer of record, which means one company covers electrical design, mechanical and thermal design, CE/FCC/IC certification and volume manufacturing. Programs range from single-unit research builds to multi-year volume production; the free feasibility review recommends the most economical route for yours.

Our typical fully custom program runs 24–25 weeks from kick-off to production release: onboarding 1 week, budgeting and contract 1 week, design 12 weeks, prototype build 2 weeks, bring-up and internal validation 3 weeks, your acceptance testing 3 weeks, and pre-production 2–3 weeks. Volume manufacturing then runs about 8 weeks per build — so first delivered production units land around weeks 32–33 for a fully custom program.

A semi-custom derivative of an existing Sixfab platform typically lands in 8–16 weeks. A configure-and-brand program is 2–6 weeks. Certification runs concurrently with design-for-manufacture rather than after it, which keeps the lab off the critical path.

Non-recurring engineering is quoted per program and billed in instalments against customer-approved design milestones — block diagram, then schematics, then PCB layout, then mechanicals. You approve each milestone before the next instalment is invoiced, so you are never more than one milestone from being able to stop.

NRE scale is driven by the number of high-speed interfaces, the enclosure and thermal complexity, the environmental rating, and the certification scope. The proposal keeps NRE and unit price as two separate numbers, so design cost never hides inside the per-unit cost. There is also a productisation route: on suitable programs Sixfab will waive the NRE at production in exchange for retaining the design IP, with a committed starting MOQ from you and optionally Sixfab branding. Feasibility is free and carries no cost obligation.

There is no hard minimum. We have run fully custom programs for single-unit research builds, and configure-and-brand orders scale down to small batches. What changes with volume is the unit economics: design, tooling and certification costs are fixed, so at low volumes they dominate the unit price and at higher volumes they disappear into it.

That is exactly what the free feasibility review lays out — the cost of each route at your volumes, including the case where ordering a standard ALPON X5 AI or Sixfab AI HAT+ and building on top is the better decision.

No. CE, FCC and IC apply to products placed on the market. A research or internal build that never goes to market can skip the certification campaign entirely, which removes both the campaign cost and its weeks from the schedule — delivery is typically at the validated-prototype stage. Custom I/O, odd form factors and rugged enclosures for lab or field experiments are normal programs here, not exceptions.

Grant-funded and institutional projects are welcome; the written feasibility findings give a procurement office a defined scope to quote against.

Yes. We run the certification campaigns at accredited labs, produce the test reports and apply compliant hardware labelling. Sixfab acts as hardware manufacturer of record and holds the Declaration of Conformity for products placed on the market under the Sixfab name. If you sell under your own brand, EU rules generally make you the manufacturer of record — the contract records the split, and we support it with the technical file and test reports. We design with pre-certified cellular modules, which removes the module-level certification burden and, in many cases, device-level acceptance by the mobile network operator as well — one of the longest and most expensive steps in a connected-product program. Which networks still require device acceptance is confirmed at feasibility, per target market.

What this does not cover: safety-critical and medical device regimes such as IEC 62304, ISO 13485 or FDA pathways. We do not hold those quality systems.

You own your foreground IP — your application, your trained models, your datasets and anything specific to your product. Sixfab retains its background and platform IP, the reusable design blocks and know-how we brought to the program.

Ownership of the custom design itself is negotiated per contract. On the standard route you pay NRE and the statement of work sets out the arrangement — including which design artefacts (schematics, layout, BOM, test specifications) transfer to you and at which milestone, and what happens to manufacturing rights if Sixfab could not continue to build. Ask for both in the proposal; they are standard topics, not special requests. On the productisation route, Sixfab waives the NRE at production and retains the design IP in exchange — a trade of ownership for cash flow that suits some programs and not others. Both options are laid out in the proposal.

An OEM arrangement means the product is designed to your specification and built for you to sell under your brand. An ODM arrangement means the manufacturer does the design work as well, and you buy the finished result. A Raspberry Pi Approved Design Partner is a separate thing entirely: a company Raspberry Pi has reviewed and approved on technical and commercial capability, giving it roadmap access, direct technical support and a named contact at Raspberry Pi.

Sixfab operates as both OEM and ODM, and is an Approved Design Partner. Practically, that combination means the design, the certification and the supply relationship sit with one company rather than three.

Yes, and it is usually the right starting point. A Tier 2 semi-custom derivative inherits a validated design and a certification baseline, so you change only what your product actually needs — connector set, I/O mix, form factor, cellular variant, thermal solution or enclosure. That typically means 8–16 weeks and delta certification testing rather than 24–25 weeks and a full campaign. If only branding, labelling and the OS image need to change, Tier 1 is faster still and requires no re-certification at all.

Yes. Board-level work — HATs, add-on boards, CM4/CM5 carrier boards and other custom PCBs — is its own service: custom Raspberry Pi HAT and hardware development. Board-level programs run much faster than complete computers: typically 6–8 weeks to a first prototype and around 12 weeks to production.

The split is simple. That service delivers the board, with enclosure work limited to customising existing off-the-shelf enclosures; this one delivers a complete, certified edge AI computer — full mechanical and industrial design, the certification campaign and volume manufacturing included. The same free feasibility review applies to both, and if you start on the wrong page we will simply route you to the right one.

Our default is DEEPX — the DX-M1 (M.2 2280) or DX-M1M (M.2 2242) — and it is the part we have shipped in our own product. Beyond it, the shortlist covers Hailo (8, 8L, 10H), MemryX (MX3), Axelera (Metis) and NXP (Ara-240), plus anything else that clears evaluation. They are all M.2 parts on the carrier, so the socket stays the same and the silicon remains a per-program decision.

Each wins somewhere different. DEEPX leads on detection throughput per watt with on-board memory and has the broadest published model zoo, which is why it is where we start. Hailo has the lowest idle power and the deepest Raspberry Pi ecosystem support, and takes semantic segmentation comfortably; Hailo-10H adds on-device generative AI with its own 4–8 GB of memory. MemryX has the fastest bring-up and explicitly documented ARM64 support. Axelera has the highest raw CNN throughput per slot. NXP’s Ara-240 is the only one with a dated, per-part longevity commitment — listed in NXP’s Product Longevity Program to April 2036, where Hailo publishes 7–10 years of supply continuity as a policy rather than a date. The choice is made at feasibility against your actual models, not against a datasheet.

DEEPX is our first option, and deliberately so. It is the silicon in our own shipped product, so a reference carrier, power tree, thermal solution and working OS image exist before your program starts, and a compile or quantisation problem gets escalated to DEEPX’s engineers rather than into a support queue. For most programs that is the fastest route to working hardware.

It is not exclusivity, and nothing in the arrangement obliges us to put a DX-M1 in your product. Hailo we have benchmarked on our own bench and design in regularly — on semantic segmentation it beat DEEPX by more than three times in the same test run, and on that workload it is what we recommend. MemryX, Axelera and NXP we have evaluated and will design in on request. If you arrive with a part already chosen, we design around it.

In short: DEEPX first because we know it best and it wins most often on the workloads we see — others whenever the measurements say otherwise.

Usually not, and the gap can be large. Vendor benchmarks are run on desktop PCs with full-bandwidth connections and generous power; a compute module offers less of both.

This is why we favour accelerators with on-board memory for bandwidth-heavy workloads, design dedicated power delivery on the carrier, and measure your models on the actual target before quoting performance. What you get at feasibility are measured numbers, not datasheet numbers.

Yes. These are all M.2 modules, so they integrate into a custom carrier over PCIe. Sixfab designs the carrier, the power delivery — including the dedicated regulator most of them need — and the thermal solution around whichever part you choose, validates the compile and quantisation path for your specific models during the free feasibility review, and handles certification of the finished assembly.

If you have already standardised on a part, we will design around it — and say so if we think it is the wrong choice. If you have not, we will recommend one and show you the measurements behind the recommendation.

This is checked before any money changes hands. The free feasibility review includes an explicit compile and quantisation check on each candidate accelerator: are your model’s operators supported by that vendor’s toolchain, and does INT8 quantisation hold accuracy at a level your application can live with? Operator coverage varies more between vendors than throughput does, and it is the most common reason a promising part gets eliminated. We also check whether the Raspberry Pi has the CPU headroom your pipeline needs outside the NPU — pre- and post-processing, video handling, your application logic. A design that clears the NPU but starves the CPU is a design that fails in the field, and it is a failure mode we see regularly.

You do. Sixfab supplies a starter BSP, firmware and OS image so the hardware boots and every interface is exercised — it is a bring-up deliverable, not a maintained software product.

Ongoing firmware and BSP maintenance, kernel and package updates, cybersecurity, secure boot and OTA patching are the customer’s responsibility. We raise this at feasibility because it is the single most common source of expectation mismatch in ODM programs, and it needs to be in your budget from the start — whether handled in-house or with a software partner. No software owner yet? Say so at feasibility and the findings will flag what your product will need.

Yes — Sixfab is listed in Raspberry Pi’s official Design Partner directory, and Raspberry Pi has publicly described Sixfab as a long-standing Design Partner. Per Raspberry Pi’s published Design Partner terms, the status provides periodic product roadmap updates, technical support including answers to schematic and layout queries, and a direct named contact at Raspberry Pi.

We monitor the BOM for end-of-life notices and issue last-time-buy notifications. Where package and pinout allow, second-source footprints are designed in from the start, and single-source risk is flagged explicitly in the feasibility report before you commit. Commercially, excess-and-obsolete and last-time-buy liability sits with the customer on parts bought against your forecast. After design freeze, any change required by a part substitution runs through a formal, priced engineering change order.

Not on any timeline that should affect a program starting now. In a May 2026 AMA, Raspberry Pi’s CEO said a Pi 6 is not expected before early 2028 and described the company’s position as believing in “the CPU as the venue for much edge AI compute”, with acceleration added externally. Raspberry Pi has given no indication of a first-party NPU, though it has not formally ruled one out. Separately, Compute Module 5 carries a production commitment to at least January 2036. The compute-module-plus-external-accelerator architecture is the one Raspberry Pi itself points at.

It is a technical compatibility screen — no design work happens at this stage. We assess whether your requirement can be met on this platform: interfaces, ports and connectors, power envelope, thermal headroom, environmental targets, certification scope, and the accelerator choice for your specific models — including the compile and quantisation check and the CPU headroom analysis described above.

We respond within 24 hours, and findings come back in writing within one week of the technical call: a yes or no, the recommended architecture, and the risks we found. A no at this stage costs you nothing.